highlights bus interface ? direct-connect peripheral/rom and dram interfaces ? support for 8-, 16- and 32-bit devices ? addressing for main memory storage: ? 192mb (403gb) ? 512mb (403ga and 403gc) ? external bus master support using the internal dram controller ? ieee 1149.1 (jtag) compatible interface, for test, debug and real-time trace support dma controller ? independent dma channels: ? four (4) (403ga and 403gc) ? two (2) (403gb) ? buffered, fly-by, memory-to-memory modes ? programmable for 8-, 16- and 32-bit transfers ? data chaining interrupt controller ? low latency interrupt handling (three cycles typical) ? six external interrupt inputs (five regular, one critical) ? dual level interrupt structure for robust debug instruction fetch, branch and dispatch unit ? four instruction prefetch queue ? branch folding and static branch prediction ? dispatches up to two instructions per cycle serial port (403ga & 403gc only) ? rs-232 serial communications ? programmable to 1.5 mb/s memory protection ? device protection ? address protection instruction and data caches ? separate 2kb instruction and 1kb data caches ? two-way set-associative ? fetch-thru instruction cache ? write-back data cache timers ? 56-bit time base (403ga and 403gb) ? 64-bit time base (403gc) ? 32-bit programmable interval timer ? fixed interval timer ? watchdog timer for system error recovery power management capability ? static low-power design ? dynamic power management and stand-by mode ? support 3.3v and 5v peripherals memory management unit (403gc only) ? memory management unit is precache (cache tags are physical addresses) ? 8 page sizes (1k-16m by powers of 4) for efficient system memory use ? 64 entry fully associative tlb with software replacement ? 16 protection zones ? efficiently designed to minimize die area product description powerpc 403ga*, 403gb* and 403gc* 32-bit risc embedded controllers combine high performance and functional integration with low power consumption. on-chip caches and integrated device control functions reduce system chip count and design complexity, while improving system throughput. these embedded controllers execute programs at sustained speeds approaching one instruction per cycle. their risc processor cores are tightly coupled to internal 2kb instruction and 1kb data caches, reducing overhead for data transfers to and from main storage. instruction queue logic minimizes pipeline stalls by managing branch prediction, branch folding and instruction prefetching. the powerpc 403gc includes an integrated mmu featuring a fully associative tlb. each entry provides translation for a memory page, which can be one of several sizes. tlb replacement is managed by software, which can employ the optimum replacement strategy for a particular application. all 403 embedded controllers implement the powerpc architecture* in ibms 0.5 m m cmos technology. these embedded controllers provide low-power 3.3v operation, with built-in stand-by mode and dynamic power management. powerpc 403ga, 403gb and 403gc embedded controllers
? international business machines corporation 1997 printed in the united states of america 1-97 all rights reserved * indicates a trademark or registered trademark of the international business machines corporation. the information contained in this document is subject to change without notice. the products described in this document are not intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. the information contained in this document does not effect or change ibms product specifications or warranties. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. all the information contained in this document was obtained in specific environments, and is presented as an illustration. the results obtained in other operating environments may vary. the information contained in this document is provided on an as is basis. in no event will ibm be liable for any damages arising directly or indirectly from any use of the information contained in this document. ibm microelectronics division 1580 route 52, bldg. 502 hopewell junction, ny 12533-6531 the ibm home page can be found at: http://www.ibm.com the ibm microelectronics home page can be found at: http://www.chips.ibm.com fax service: (415) 855-4121 *07gk10308002* gk10-3080-02 powerpc 403ga, 403gb and 403gc specifications technology 0.5 m m cmos, 3 levels of metal number of transistors ~ 585,000 (403ga), ~ 500,000 (403gb), ~ 635,000 (403gc) max case temp. range 0 c to 85 c signal i/os 126 (403ga and 403gc) 104 (403gb) power supply 3.3v 5% (support for 5v i/os) performance 56 mips (dhrystone2.1) @ 40mhz (403ga and 403gc) 39 mips (dhrystone2.1) @ 28mhz (403gb) performance/power 175 mips/w (dhrystone 2.1) (403ga and 403gc) 186 mips/w (dhrystone 2.1) (403gb) power dissipation (typ.) 320 mw @ 40mhz (403ga and 403gc) 210 mw @ 28mhz (403gb) packaging 160-pin plastic quad flat pack (403ga and 403gc) 128-pin thin quad flat pack (403gb) frequency 25, 33 or 40mhz (403ga and 403gc) 28 mhz (403gb) the powerpc 403ga, 403gb and 403gc are supported by ibm and over 75 select third-party vendors in the powerpc embedded tools* program. this program offers a full range of embedded development tools, including compilers, debuggers, real-time operating systems, emulators, logic analyzers, and evaluation boards. 4-ch (403ga & 403gc ) dma controller serial port port jtag dram controller i/o controller bus interface unit sram, rom, i/o controls controls address bus data bus on-chip peripheral bus dram interrupt controller risc execution unit cache unit instruction cache unit data timers memory management unit (403gc only) (403ga & 403gc) 2-ch (403gb) trace port (403ga & 403gc)
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